1. Field of the Invention
The present invention relates to a DQPSK (differential quadrilateral phase shift keying) delay detection circuit, and in particular to a DQPSK delay detection circuit that can produce stable regenerative clocks and also minimize the jitter of regenerative clocks.
2. Description of the Prior Art
FIG. 6 is a block diagram showing the configuration of a DQPSK delay detection circuit, reported in "Configuration and Characteristics of .pi./4 Shift QPSK Baseband Delay Detector", in Autumn national convention, B-300, 1990 Institute of Electronics, Information and Communication Engineers.
The above mentioned DQPSK delay detection circuit, hereafter referred to as DQPSK delay detection circuit(51), is comprised of a semi-synchronous detector(2), a low-pass filter(3), an A/D converter(4), a data delay unit(55), an operation unit(56), a judging unit(7), and a clock pulse generator(58).
The data delay unit(55) has a shift register T. The clock pulse generator(58) is provided with a clock signal generator circuit(9) and a BTR (bit timing recovery) unit (60). Clock signal generator circuit(9) of the clock pulse generator(58) supplies a 32f clock signal (a signal with a frequency 32 times as high as the symbol rate frequency f) to the A/D converter(4), to the data delay unit(55) and to the operation unit(56). The BTR unit(60) of the clock pulse generator(58) supplies a 2f clock signal (a signal with a frequency two times as high as the symbol rate frequency f) to the judging unit(7).
In the above mentioned DQPSK delay detection circuit(51), the semi-synchronous detector(2) synchronously detects an in-phase signal X and quadrature signal Y from the input signal. The detected in-phase signal X and quadrature signal Y are passed through the low-pass filter(3) and inputted to the A/D converter(4). The A/D converter(4) samples this inputted signal at 32f frequency and performs an analog to digital conversion with six quantization bits and then passes this signal to the data delay unit(55) and to the operation unit(56).
Shift register T of the data delay unit(55) delays the output of the A/D converter(4) by a time equivalent to one time slot and passes this one time slot delayed signal to the operation unit(56). The operation unit(56) calculates orthogonal signals I and Q containing code bit information from the present output signal of the A/D converter(4) and the above mentioned one time slot delayed signal of the data delay unit(55). The BTR unit(60) of the clock pulse generator(58) reproduces a 2f clock signal in accordance with the timing of the sign bit of the Q signal from the operation unit(56). Judging unit(7) selects a point with the largest eye aperture among 32 sample points during one time slot on the basis of the 2f clock signal regenerated by the BTR unit(60), and performs parallel-serial conversions before outputting the data.
FIG. 7 is an example circuit of the BTR unit(60). Zero-cross detection circuit(61) outputs a signal corresponding to "1" when it detects a zero-cross point of the reversed sign bit of the Q signal. When the zero-cross detection circuit(61) outputs a signal corresponding to "1", the window setup circuit(62) outputs a signal "1" during a predetermined period of time. This predetermined period is a period of time ranging from the time slightly shorter than the symbol rate period 1/f to the time slightly longer than the same.
If both the zero-cross detection circuit(61) and the window setup circuit(62) output a signal "1", then the AND circuit(63) also outputs a signal corresponding to "1". Synchronized with the output signal "1" of the AND circuit(63), DPLL(64) outputs a 2f clock signal. In the above mentioned BTR unit(60), an I signal may be used as an input instead of the Q signal.
In the conventional DQPSK delay detection circuit 51, BTR unit(60) reproduces a 2f clock signal on the basis of the timing when the reversed sign bit of the Q signal is reversed. However when the phase shift in the I/Q coordinates is the same as in the case when the data consists of a repetition of bit chains 0101 . . . , and 0000 . . . , the zero-cross detection circuit(61) cannot properly detect the zero-cross point because there is no change in the sign bit of the Q signal. In such cases there is a disadvantage that the DPLL(64) cannot execute the synchronous drawing and thus failing the reproduction of a 2f clock signal.
Q signal (long dashed line) and an I signal (short dashed line) sampled at a frequency 32 times the symbol rate frequency f are shown in FIG. 8 and FIG. 9. It can be seen that the variation in zero-cross points ranges over 40% of the symbol rate period 1/f. Hence there is a disadvantage that a 2f clock signal with large Jitters decreases the reliability of data demodulation.